This application pertains to circuits and methods for shifting voltage levels of a signal.
It is known in the art to have a first portion of an electronic system use a first set of rail (e.g., power supply) voltages to communicate digital signals and a second portion of the system use a second set of rail voltages to communicate digital signals. Such a system typically comprises level shifter circuits to shift the voltage levels of signals from the first set of rail voltages to the second set of rail voltages so that the first portion of the system can communicate with the second portion of the system. FIG. 1A illustrates a prior art level shifter circuit 1 for receiving input signals IN1 and IN1′ having a first pair of rail voltage values and generating therefrom output signals OUT1 and OUT1′ having a second pair of rail voltages. (As used herein, signal IN1′ is the logical inverse of signal IN1 and signal OUT1′ is the logical inverse of signal OUT1. The apostrophe indicates a logical inverse.)
Signals IN1 and IN1′ are characterized by rail voltages VSS and VDDL (0 and 0.7 volts, for example), and signals OUT1 and OUT1′ are characterized by rail voltages VSS and VDDH (0 and 1.2 volts, for example). When signal IN1 is high, transistor T1 is on, signal OUT1′ is low, transistor T4 is on, and signal OUT1 is high. When signal IN1 is low, the opposite is true.
FIG. 1B illustrates a second prior art circuit 2 for receiving signals IN1 and IN1′ and converting them to output signals OUT1 and OUT1′. There are several problems with circuits 1 and 2.
Regarding circuit 1, signal IN1 transitions from VSS to VDDL and signal IN1′ transitions from VDDL to VSS. Prior to this transition, transistors T1 and T4 are off, transistors T2 and T3 are on, signal OUT1′ is high (i.e. at voltage VDDH), and signal OUT1 is low. At the time of transition, signal IN1 turns on transistor T1, pulling signal OUT1′ low and thereby turning on transistor T4. Eventually, the voltage at OUT1 rises to voltage VDDH and turns off transistor T3. Unfortunately, there is a time window during which transistors T2 and T4 are both on, which results in contention. The contention slows the completion of switching and draws excess current and therefore consumes excess power. A similar window occurs in transistors T1 and T3 when signal IN1 transitions from voltage VDDL to voltage VSS and signal IN1′ transitions from voltage VSS to voltage VDDL.
If the high voltage of signal OUT1 (i.e. VDDH) is much larger than the high voltage of signals IN1 and IN1′ (voltage VDDL), transistor T1 becomes weaker than transistor T3. At some point, transistor T1 will be unable to resolve the contention, and will fail to pull signal IN1′ sufficiently low. This mechanism sets operation limits of circuits 1 and 2. Thus, one important feature of a successful level shifter design is to accommodate a high VDDH to VDDL ratio. Another important feature of a level shifter design is to minimize contention between the pull-up PMOS transistors T3 and T4 and the pull-down NMOS transistors T1 and T2, and cause the level shifter circuit to latch as quickly as possible. Thus, it would be desirable to pull signal OUT1 high to turn off transistor T3 more quickly to minimize switching delay and switching current. It is also desirable to minimize DC current.
Circuit 2 also exhibits problems. For example, when signal IN1 is high, both transistors T5 and T7 are on, thereby causing circuit 2 to draw excessive current and consume excessive power.